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In the rapidly evolving world of hardware security, developing metrics for evaluating the security improvements of hardware designs is important. This work examines the prevailing threat model for secure analog-to-digital converter (ADC) architectures and explains how signal-to-noise ratio (SNR), root-mean-square error (RMSE), and bit-wise accuracy (BWA) are used to evaluate security improvements. The existing metrics are mathematically related through the proposed Proxy ADC framework. The proposed SNR-RMSE and BWA-RMSE relationships are validated using a power side-channel attack on a commercial ADC. The SNR-RMSE relationship achieves an average percent error of 1.69% across four trials, while the BWA-RMSE relationship achieves an average of 7.97%. Using results from past secure ADC works allows for additional demonstrations of the relationships. These relationships can estimate accuracy in a realistic attack scenario where ADC outputs cannot be measured to verify the evaluation, and recontextualize the metrics of standard ADC design for hardware security. Furthermore, the Proxy ADC framework allows for comparison of tradeoffs between designs’ security and efficiency, revealing trends to leverage for future secure architectures.